The invention relates to a method and circuit for reducing noise and charge injection errors and improving DC precision in auto-zeroed circuits.
In nulling amplifiers of auto-zero circuits such as the one shown in FIGS. 1A and 1B, low input-referred noise is achieved by maximizing the transconductance (gm) ratio of a pair of main input transistors to that of a pair of nulling transistors. The gm of the pair of main input transistors is limited by their physical size and by current consumption limitations of the auto-zero circuit and the nulling amplifier thereof. The gm ratio of the pair of main input transistors to that of the nulling pair of transistors may be maximized by decreasing the gm of the nulling pair, but if the gm of the nulling pair is decreased too much, the DC precision of the nulling amplifier and the DC precision of the auto-zeroed amplifier circuit is worsened by gain error effects in the nulling amplifier. In the past, certain limitations of the ratio of the gm of the pair of main input transistors pair to the gm of the nulling pair of transistors for auto-zeroed amplifiers have been accepted as a fundamental design constraint. Specifically, because of constraints on the quiescent current consumption of integrated circuit chips containing auto-zeroed amplifiers, it has been commonly accepted that the ratio of the gm of the pair of main input transistors to the gm of the nulling pair of transistors should be roughly 10. It has been commonly accepted that a larger ratio would result in unacceptably large chip size and power consumption.
Thus, there is an unmet need for an improved way of reducing the input-referred noise of the nulling amplifier of an auto-zeroed amplifier circuit. There also is an unmet need for an improved way of reducing the input-referred noise of the nulling amplifier of an auto-zeroed amplifier circuit while maintaining a low input offset voltage of the nulling amplifier.
There also is an unmet need for an improved way of reducing the input-referred noise of the nulling amplifier of an auto-zeroed amplifier circuit without substantially increasing quiescent current consumption, and/or cost of the auto-zeroed amplifier circuit while maintaining a low input offset voltage of the nulling amplifier.
Accordingly, it is an object of the invention to provide an improved way of reducing the input-referred noise of the nulling amplifier of an auto-zeroed amplifier circuit.
It is another object of the invention to provide an improved way of reducing the input-referred noise of the nulling amplifier of an auto-zeroed amplifier circuit while maintaining a low value of the corrected input offset voltage of the nulling amplifier.
It is another object of the invention to provide an improved way of reducing the input-referred noise of the nulling amplifier of an auto-zeroed amplifier circuit without substantially increasing power dissipation, size, and/or cost of the auto-zeroed amplifier circuit while maintaining a low input offset voltage of the nulling amplifier.
Briefly described, and in accordance with one embodiment thereof, the invention provides a nulling amplifier (52A) for an auto-zeroed amplifier that includes a first differential stage including first (3) and second (16) input transistors and a second differential stage including first (18) and second (19) nulling transistors coupled to drains of the first and second input transistors and to a folded cascode circuit (48) coupled to an output stage (59). A gain boost circuit controls the output resistance of the auto-zeroed amplifier. The gm ratios of the first and second input transistors and the first and second nulling transistors have values which establish a predetermined low input-referred noise level in the nulling amplifier, and the gain boost circuit provides high gain resulting in low gain error and thereby allows the offset voltage of the nulling amplifier to be reduced.
In the described embodiment, a nulling amplifier (52A) includes a first differential stage including first (3) and second (16) input transistors and a first tail current source (38) coupled to sources of the first and second input transistors. A switching circuit (50) selectively couples a gate of the second input transistor (16) to either a first input signal (Vin+) or to a gate of the first input transistor (3) in response to a control signal (xcfx86), a second input signal (Vinxe2x88x92) being coupled to the gate of the first input transistor. The second differential stage includes first (18) and second (19) nulling transistors, a second tail current source (39) being coupled to sources of the first and second nulling transistors, a drain of the first nulling transistor being coupled to the drain of the second input transistor, a drain of the second nulling transistor being coupled to the drain of the first input transistor. A first hold capacitor (C3) is coupled between a gate of the first nulling transistor and a first reference voltage, and a second hold capacitor (C4) is coupled between a gate of the second nulling transistor and the first reference voltage. First (69A) and second (69B) switches couple the gates of the first and second nulling transistors to receive first (Voutxe2x88x92) and second(Vout+) output signals coupled to an output stage (59) in response to the control signal (xcfx86).
A folded cascode circuit (48) has an input coupled to the drains of the first (3) and second (16) input transistors and an output coupled to the input of the output stage (59). The folded cascode circuit (48) includes a first low side constant current source transistor (7) having a drain coupled to the drain of the second input transistor (16) and to a source of a first cascode transistor (8), and a second low side constant current source transistor (41) having a drain coupled to the drain of the first input transistor (3) and to a source of a second cascode transistor (9). The gain boost amplifier circuitry (113,117) includes a low side gain boost amplifier (113) including a first gain boost amplifier output transistor (11) coupling the drain of the first low side constant current source transistor (7) to the source of the first cascode transistor (8) and a second gain boost amplifier output transistor (10) coupling the drain of the second low side constant current source transistor (41) to the source of the second cascode transistor (9).
The folded cascode circuit (48) also includes a first high side constant current source transistor (4) having a drain coupled to the drain of the first cascode transistor (8), and a second high side constant current source transistor (20) having a drain coupled to the drain of the second cascode transistor (9).
The gain boost amplifier circuitry (113,117) also includes a high side gain boost amplifier (117) including a third gain boost amplifier output transistor (1) coupling the drain of the first high side constant current source transistor (4) to the drain of the first cascode transistor (8) and a fourth gain boost amplifier output transistor (2) coupling the drain of the second high side constant current source transistor (20) to the drain of the second cascode transistor (9).
The low side gain boost amplifier (113) includes a first feedback input (FBI) coupled to the drain of the first low side constant current source transistor (7) and a second feedback input (FB2) coupled to the drain of the second low side constant current source transistor (41). The high side gain boost amplifier (117) includes a first feedback input (FB1) coupled to the drain of the second high side constant current source transistor (20) and a second feedback input (FB2) coupled to the drain of the first high side constant current source transistor (4).
A common mode feedback circuit (47) is coupled to the first and second switches and the first (4) and second (20) high side constant current source transistors to produce a common mode level of the first (Voutxe2x88x92) and second (Vout+) output signals.